FIG. 1 shows a conventional physical layer transceiver 10 (or PHY device), configured to operate in a storage network. Transceiver 10 generally comprises a transmitter 20, a receiver 30, a digital timing loop 40 and a finite state machine 50. Digital timing loop 40 receives a digital receiver clock signal RXCLK from receiver 30 and (optionally) a digital transmitter clock signal TXCLK from transmitter 20, and outputs multi-bit adjustment/control signals TXDPHER and RXDPHER to transmitter 20 and receiver 30, respectively. In one embodiment, digital clock signal TXCLK has a frequency about double that of digital clock signal RXCLK. Digital timing loop 40 also receives a control signal CNTRL from finite state machine 50, and provides an active “phase locked” status signal PHLOCK to finite state machine 50 under appropriate conditions. Digital timing loop 40 functions to keep timing signals in the receiver 30 locked to and in phase with an appropriate reference signal. Finite state machine 50 also functions to reset transmitter 20 and receiver 30 on power up and to reset digital timing loop 40 under appropriate conditions.
In one application, transmitter 20 transmits a serial data stream generated from a coupled storage device to a network, and receiver 30 receives a serial data stream from the network for subsequent processing (e.g., conversion to a parallel data stream and storage in the coupled storage device). Transmitter 20 and receiver 30 also receive an internal reference clock signal from a phase locked loop (PLL) on the PHY device (see PLL 114 in FIG. 2) for generating the respective digital transmitter and receiver clock signals that control data transfer and processing functions.
Referring now to FIG. 2, one function of a PLL 114 is to generate one or more periodic signals, which may have multiple phases. Furthermore, functions of clock data recovery (CDR) circuitry include (i) selecting an appropriate phase of a periodic signal (or “clock”) from the PLL to lock to the incoming data stream and (ii) generating or producing a recovered clock from the phase-locked PLL clock. Thus, CDR circuitry may provide a number of control and/or status signals to digital timing loop 40, including signals UP and DN, which instruct the digital timing loop 40 to speed up or slow down the recovered clock.
One approach to locking a recovered clock to a reference clock is shown in FIGS. 2 and 3. FIG. 2 shows clock adjustment circuitry 100 within the digital timing loop 40 of FIG. 1. CDR circuitry 100 generally comprises phase adjustment circuitry 104 and first integrator 106. A “receiver loop” comprises the summed output from phase adjustment circuitry 104 and integrator 106 in digital timing loop 40, and a first interpolator or reference clock phase selection circuit 116 and a phase detector block 102 in receiver 30. Integrator 106 feeds a multi-bit phase error correction signal RXDPHER to interpolator 116, which selects an appropriate phase of a multi-phase reference clock to input into phase detector block 102 in receiver 30. Phase detector block 102 also generates the signals UP and DN. In one embodiment, phase detector block 102 comprises four parallel phase detectors, each of which outputs separate UP and DN signals (see FIG. 1) that are then input into appropriate logic (e.g., “majority vote” logic) to determine the state of the up/dn signal input into phase adjustment circuitry 104.
In the diagram of FIG. 2, the recovered clock signal RXCLK is produced by receiver 30. Phase detector 102 in receiver 30 receives a serial data stream RX from an external source in the network, and passes a received data signal RXD to data processing circuitry in the PHY device. Phase detector 102 also provides clock signal RXCLK recovered from the serial data stream. Clock adjustment circuitry 100 is configured to correct phase error or phase offset in the recovered clock RXCLK. PLL 114, which receives a reference frequency from an external crystal oscillator XTL, provides a “master” or reference clock signal to receiver 30 and transmitter 20, from which the respective multi-phase reference clocks are generated. Phase error correction signal RXDPHER is fed into a multiplexer in interpolator 116 to select an appropriate phase of the PLL reference clock for input into phase detector 102. When the incoming data transmission rate is the same as the reference clock signal and the clock data recovery circuitry is in equilibrium, then the value of phase error correction signal RXDPHER remains constant, the same phase of the PLL reference clock is continuously selected, and the PLL reference clock is phase locked to the incoming data. If the incoming data transmission rate changes, the phase detector will detect an offset between the incoming data stream and the selected PLL reference clock, the value(s) of phase error correction signal RXDPHER will change, and a different phase of the PLL reference clock will be selected to adjust it closer to or into alignment with the phase of the incoming data signal.
FIG. 3A is a simplified diagram of conventional phase adjustment circuitry 104 in the clock adjustment circuitry of FIG. 2. A phase adjustment control signal up/dn is output from receiver phase detector 102 (or, alternatively, UP/DN logic in clock adjustment circuitry 100). In one embodiment, phase adjustment control signal up/dn is a three-level signal (i.e., having +1, 0, and −1 states). Phase adjustment circuit 104 comprises a phase adjustment path 120 and a phase-frequency adjustment path 122 parallel thereto, both of which receive the phase adjustment control signal up/dn. Phase adjustment path 120 generally comprises a multiplier 130, and phase-frequency adjustment path 122 generally comprises a multiplier 132 and an integrator 134. Multiplier 130 also receives a phase adjustment coefficient μp, and multiplier 132 receives a phase-frequency adjustment coefficient μf. These coefficients are essentially bias signals generated by conventional bias generator circuitry in accordance with predetermined design criteria, applied to multipliers 130 and 132 to provide predetermined and/or controlled effects on the phase adjustment of the recovered clock signal RXCLK. The outputs of the two adjustment paths are summed by adder 136.
FIG. 3B shows a data waveform and set of equations for illustrating the operation of the clock phase adjustment circuitry of FIG. 3A. In FIG. 3B, symbols “ex” and “cx” represent transitions of certain defined phases of the PLL reference clock (also see FIG. 6 and the corresponding description below). The edge, or “e,” reference clock is designed to have transitions that generally coincide with transitions in the data stream, and the center, or “c,” reference clock is designed to have transitions that occur during excursions or voltage level swings representing binary logic values in the individual data bits.
The up/dn signal (or alternatively, an UP and/or DN signal) is generated by sampling and comparing certain data points. At reference clock transitions e1 and c1, data is sampled and logically compared. If e1≈c1, then a transition (or phase change) has occurred in the data stream within a fraction of a data bit length. (Herein, a “data bit length” refers to the length of time for receiving one bit of data; e.g., in a data stream having a transmission rate of 1 Gb/sec, a data bit length is 1 ns.) As a result, phase detector 102 asserts an active do signal (e.g., a −1 value), and an appropriate adjustment is made to the RXDPHER signal to select a different phase of the PLL reference clock, thereby moving its phase closer to alignment with the data stream. This process may be repeated until the PLL reference clock and the incoming data stream are phase-aligned (i.e., the same transition occurs in each signal within an “alignment window,” or period of time during which no difference in phase can be detected). Also, at reference clock transition e2, the data is sampled and compared to the data value at reference clock transition c1. If c1≈e2, then a transition has occurred in the data stream within about one data bit length, but between excursions in the data bits. As a result, phase detector 102 asserts an active up signal, and appropriate control signals are applied to the RXDPHER signal to select a different phase of the PLL reference clock, thereby moving its phase closer to alignment with the data stream. This process may also be repeated until the two clocks are phase-aligned. Ideally, there is no bias between up and dn assertions; i.e., the amount of time that up is asserted is roughly equal to the amount of time that dn is asserted.
Although phase adjustment circuit 104 includes a phase-frequency adjustment path 122, the term “phase-frequency” is more of a label than a completely accurate characterization of the circuit. For example, phase detector 102 only detects phase differences, and not frequency differences, between the PLL reference clock and the data stream. Furthermore, the logic that generates phase adjustment control signal up/dn can only determine whether a phase transition has occurred. This logic cannot provide any information about the frequency of the recovered clock RXCLK. Consequently, designers must assume and/or infer certain relationships between phase differences and frequency differences, and make different adjustments for perceived frequency differences. For example, phase-frequency adjustment path 122 includes an integrator 134, whereas phase adjustment path 120 does not. Also, the coefficients input into multipliers 130 and 132 typically differ from each other. The resultant output from phase-frequency adjustment path 122 is generally considered representative of a frequency offset between the transmission rate of incoming data and the recovered clock (or a multiplied and/or divided equivalent thereof).
However, this approach is not 100% effective for correcting frequency offsets in a clock signal recovered from a data stream. There is a potential error condition in the clock data recovery loop of FIG. 2 where the frequency offset between the reference clock and the incoming data stream is sufficiently large to cause the loop to diverge. In fact, under some conditions, a difference in the frequencies of the recovered clock signal and data stream will increase as the clock adjustment circuitry adjusts their phases into alignment.
As is known in the art, the data stream coming into the receiver 30 may be intermittent, and its rate may vary slightly from source to source. Occasionally, the rate from a single source may vary as well. Where the changes or disparities in transmission rates (or differences between the data transmission rate and the PLL frequency) lead to relatively large offsets in the phase of the recovered clock, the phase detector 102 and phase-frequency adjustment circuitry 104 will push the phase of the recovered clock in one direction in order to align it with the PLL. However, at sufficiently high offsets (e.g., about 1.5% or greater), the phase adjustment will actually change the frequency of the recovered clock in the direction away from convergence. In such a case, a runaway condition may result, leading to device failure and a need to reset the device. Therefore, a need exists to solve this potential failure mechanism.
As network speeds increase, the potential failure modes associated with clock data recovery make designing stable, flexible, adaptable and effective clock data recovery circuitry challenging. Thus, what is needed is an approach to high-speed clock data recovery designs that minimize or prevent the potential nonconvergence/clock runaway problem described above, preferably with minimal or no changes to existing designs and logic, and minimal additional circuitry to be added thereto.